As critical dimensions in semiconductor devices are reduced, the maximum voltage (e.g., power supply voltages) used by such devices are also scaled. For example, a maximum power supply voltage, Vdd, used by semiconductor device scales with gate-oxide thickness. The scaling of termination voltages, voltage swings and/or a common mode voltage used in signaling between semiconductor devices or ICs, however, often lags behind the changes in the power supply voltages. As a consequence, it is increasingly difficult to communicate between two semiconductor devices having different manufacturing process generations using the same signaling technology, with a fixed termination voltage, voltage swing and/or common mode voltage.
In the case of a semiconductor memory, such as dynamic random access memory (DRAM), communicating between semiconductor devices having different signaling levels poses challenges in the design of an input-output (I/O) interface in a controller. For example, the I/O device signaling levels may be higher than those in the core of the memory device. In addition, in a bi-modal design, such as when the controller needs to communicate with both 1.2V (XDR) and 1.8V (DDR2) DRAM, circuits in the I/O interface must be able to handle signals at both of these voltages with different voltage swing and common mode requirements.
To overcome these limitations, there is a need for an improved I/O interface signaling technology for use in communication between semiconductor devices.
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